Flash memory up to the 0.13 μm generation employ FG memory elements that use floating gates (FG) as electron-capture layers that save information by capturing electrons. In addition, miniaturization of FG memory elements chiefly involved the reduction of cell area and thinning of insulating films. In flash memory of the 90-nm generation and beyond, however, thinner insulating films are problematic from the standpoint of retaining information. As a result, trap-type memory elements that hold information by trapping electrons in an insulating film are receiving attention in place of FG memory elements.
A trap-type memory element has the advantages of enabling a greater reduction of the equivalent oxide thickness equivalent thickness than an FG memory element and having a simpler device configuration than an FG memory element. The reduction of the equivalent oxide thickness equivalent thickness includes the thinning of tunnel oxide films.
A trap-type memory element uses the locality of electrons to enable writing of two or more bits of information per cell. As a result, a trap-type memory element is able to reduce cell area per bit and can decrease the fabrication costs of flash memory.
FIG. 1 is a sectional view of an example of the configuration of a trap-type memory element. As shown in FIG. 1, in a trap-type memory element, gate electrode 5 is formed to sandwich trap insulating film 4 on the channel region of p-type semiconductor substrate 1. In addition, n-type source-drain regions 2 and 3 are formed at two sides of gate electrode 5 in p-type semiconductor substrate 1. Source-drain regions 2 and 3 are diffusion regions, one being a source and the other being a drain. In source-drain regions 2 and 3, the source and drain are switched in the write state and read state. In addition, the vicinities on both ends of gate electrode 5 are the electron accumulation regions of memory nodes A and B. A layered construction of oxide film/nitride film/oxide film is normally used for trap insulating film 4.
FIG. 2 is an explanatory view for describing an example of the operation of a trap-type memory element.
When memory node A is to be placed in the write state, a positive voltage is applied to each of source-drain region 2 and gate electrode 5. In this case, channel hot electrons (CHE) are produced in the vicinity of memory node A and the electrons are implanted into trap insulating film 4 in the vicinity of memory node A. Electrons are thus accumulated in trap insulating film 4 and memory node A enters the write state.
When memory node A is to be placed in the delete state, a positive voltage is applied to source-drain region 2 and a negative voltage is applied to gate electrode 5. In this case, hot holes are produced as a result of interband tunneling in the vicinity of memory node A. These hot holes are implanted into trap insulating film 4, whereby the electrons that were accumulated in trap insulating film 4 are neutralized and memory node A enters the delete state.
When information is to be read from memory node A, a positive voltage is applied to both source-drain region 3 and gate electrode 5, and the current value between source-drain regions 2 and 3 is read. When electrons are accumulated in memory node A, flat band voltage in the vicinity of source-drain region 2 that is the source shifts towards positive, whereby the current value between source-drain regions 2 and 3 drops. When this current value is less than a predetermined value, memory node A is determined to be in the write state, and when this current value is equal to or greater than the predetermined value, memory node A is determined to be in the delete state, the state of the memory being thus identified.
When memory node B is to be placed in the write state, a positive voltage is applied to source-drain region 3 and gate electrode 5, whereby channel hot electrons are produced in the vicinity of memory node B and electrons are implanted and accumulated in trap insulating film 4 in the vicinity of memory node B. When memory node B is to be placed in the delete state, a positive voltage is applied to source-drain region 3 and a negative voltage is applied to gate electrode 5, whereby hot holes resulting from interband tunneling are generated in the vicinity of memory node B and accumulated electrons are neutralized. On the other hand, when memory node B is to be placed in the read state, a positive voltage is applied to each of source-drain region 2 and gate electrode 5 and the current value between source-drain regions 2 and 3 is read.
However, because a hot carrier is implanted into trap insulating film 4 when information is read in a trap-type memory element of this type, a problem (Read Disturb) arises in which the amount of electrons that are accumulated changes as the number of times information is read increases, resulting in a change of the information that is stored.
More specifically, as shown in FIG. 2, when information is to be read from memory node A, a positive voltage is applied to source-drain region 3 and gate electrode 5, but a small number of channel hot electrons are produced in the vicinity of memory node B. As a result, when memory node B is in the delete state and information is read from memory node A a large number of times, the delete state changes to the write state and memory node B malfunctions. When information is read from memory node B a great number of times, the state of memory node A changes.
Writing and deletion of information is carried out by the implantation of hot electrons and hot holes into trap insulating film 4, and this leads to the problem of the deterioration of trap insulating film 4 and the deterioration of the capability to retain electrons when the writing and deletion of information is carried out repeatedly. This problem occurs because trap-type insulating film 4 also serves as the insulating film of gate electrode 5.
To fundamentally solve this problem, trap insulating film 4 that is the storage area must be isolated from the channel region in which the hot carrier is produced. However, when trap insulating film 4 is isolated from the channel region in which the hot carrier is produced, the trap-type memory is unable to accumulate electrons and therefore cannot record information.
This occurrence of read Disturb and the deterioration of the retaining capability results in the decrease of reliability in a trap-type memory element.
A resistance-changing memory element is a memory element that provides a solution to this problem of low reliability, and resistance-changing memory elements are now receiving attention as flash memory memory elements of the 65 nm generation and beyond.
FIG. 3 is a sectional view showing an example of the construction of a resistance-changing memory element. In FIG. 3, the resistance-changing memory element includes: semiconductor substrate 11 in which drain region 12 and source region 13 are formed; insulating film 16 that is formed on semiconductor substrate 11; gate electrode 15 that is formed on insulating film 16; resistance-changing layer 17 that is connected to drain region 12; and wiring layer 18 that is connected to resistance-changing layer 17. Insulating film 16 is formed of a material that does not trap electrons.
In resistance-changing layer 17, an MIM (Metal/Insulator/Metal) structure is typically used in which a transition metal oxide such as nickel oxide (NiO), vanadium oxide (V2O5), zinc oxide (ZnO), titanium dioxide (TiO2), or tungsten trioxide (WO3) is sandwiched by a metal such as titanium nitride (TiN), platinum (Pt), or ruthenium (Ru).
FIG. 4 is a block diagram showing an example of the configuration of a memory cell array that uses resistance-changing memory elements. This memory cell array is described in, for example, Patent Document 1.
As shown in FIG. 4, in a memory cell array that uses resistance-changing memory elements, column decoder 31 is connected to n bit-lines BL1, BL2, BL3, . . . , BL(n), and word decoder 32 is connected to m word lines WL1, WL2, . . . , WL(m).
Each of bit-lines BL1-BL(n) is arranged to intersect with each of word-lines WL2-WL(m), and resistance-changing memory elements 33 are arranged at these intersections. Here, wiring layer 18 of resistance-changing memory element 33 is connected to a bit-line, and gate electrode 15 of resistance-changing memory element 33 is connected to a word-line. FIG. 4 further shows variable resistance 34 realized by resistance-changing layer 17.
Writing and deletion of information to this resistance-changing memory element 33 is realized by applying a positive voltage to wiring layer 18 and gate electrode 15 and by adjusting the current that flows from source region 13 by way of drain region 12 to resistance-changing layer 17. Reading information from resistance-changing memory element 33 is realized by applying a positive voltage to wiring layer 18 and gate electrode 15 and reading the current that flows between drain region 12 and source region 13 that changes according to the resistance value of resistance-changing layer 17. However, the voltage that is applied to wiring layer 18 during reading is a positive voltage and is lower than the voltage applied to wiring layer 18 during writing.
When a resistance-changing memory element is used, resistance-changing layer 17 that is the storage region does not further serve as the gate insulating film of gate electrode 15, and further, is sufficiently separated from the channel region. As a result, the problem of reduced reliability such as the read Disturb that results from hot electrons and hot holes and the drop in retaining capabilities can be solved. Further, the elimination of the need to generate a hot carrier during deletion enables a reduction of the operating voltage.    Patent Document 1: JP-A-2004-185754